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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
Advanced Information
November 2000
DESCRIPTION
The 78P2253 is a transceiver IC designed for 139.264Mbit/s (E4) or 155.52Mbit/s (OC-3, STS-3 or STM-1) transmission. It is used at the interface to a 75 coaxial cable using CMI coding or a fiber optic module. Interface to digital framer circuits is accomplished via a serial PECL or parallel CMOS interface. The transmitter includes a PLL to multiply the reference clock to the transmission frequency. The receiver provides adaptive equalization for accurate clock and data recovery. The 78P2253 is built in a BiCMOS technology for high performance and low power operation. It operates with a 3.3V or 5V power supply and is packaged in a 64-pin TQFP.
FEATURES
* 139.264Mbit/s or 155.52Mbit/s interface for CMI coded transmission using 75 coaxial cable Compliant with ITU-T G.703, G.823 jitter tolerance, Telcordia TR-NWT-00253 Integrated Clock Recovery Unit (CRU) Serial PECL Interface Four and Eight bit Parallel CMOS Interfaces PECL Interfaces for connection to Fiber Optic Modules for SONET OC3 applications Adaptive Equalization Integrated Clock Multiplier PLL Advanced BiCMOS Process
* * * * * * * *
BLOCK DIAGRAM
HUB/HOST PAR/SER E4/SONET 8BIT/$BIT CM I/ECL
XTAL1
XTAL2
CKIN
Crystal Oscillator
Clock Generator
Binary to CMI
CMIOUTP CMIOUTN
TXCK TXCKP,N RLBACK TXDTP,N TXDT[7:0] ECLOUTP ECLOUTN
ECLINP ECLINN
RXDTP,N RXDT[7:0] RXCKP,N RXCK
CMI to Binary
Clock Recovery
Adaptive Equalizer
CMIINP CMIINN
Bias
Signal Detector
RFO
LLBACK
LOS
LF
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
FUNCTIONAL DESCRIPTION
The 78P2253 contains all the necessary transmit and receive circuitry for connection between 139.264Mbit/s or 155.52Mbit/s signals and digital Framer/Deframer ICs. Operating Rate The 78P2253 has a variety of operating modes and rates. They are summarized in the tables below. More detailed descriptions can be found in the sections that follow.
Standard E4/SONET CMI/ECL Rate (Mbit/s) OC-3 STM1 optic STS-3 STM-1 Coax 1 E4 1 0 1 139.264 139.264 17.408 17.408 ECL CMI 0 1 155.52 19.44 CMI 0 0 155.52 Reference Frequency (MHz) 19.44 ECL Active I/O
matching resistors. In CMI mode the transmitter shapes the transmit pulses to meet the appropriate template and the adaptive equalizer corrects the received signal for dispersive attenuation. The ECLOUTP and ECLOUTN pins are inoperative and should be left open. When the CMI/ECL pin is low the chip is in ECL mode and a fiber optics transceiver is used. The output data signal from the pins ECLOUTP and ECLOUTN have PECL levels. In this mode, the CMI pins are inoperative and should be left open. The CMI encoder and decoder are disabled. TRANSMITTER OPERATION The transmitter section generates an analog signal for transmission through a transformer onto the coaxial cable or fiber optic module. When the PAR/SER pin is low the chip is in serial mode. Serial data is input to the 78P2253 on the TXDTP and TXDTN pins at PECL levels. The data is timed with the clock generated by the 78P2253 on the TXCKP and TXCKN pins. In this mode the 8BIT/$BIT pin is ignored. When the PAR/SER pin is high the chip is in parallel mode. Parallel data is in put to the 78P2253 on the TXDT[7:0] pins. The input data is timed with the clock output from TXCK. When 8BIT/$BIT is high all eight bits of TXDT[7:0] are used and the clock frequency at TXCK is one-eighth the standard frequency. When 8BIT/$BIT is low the lower four bits, TXCK[3:0] are used and TXCK is one-fourth the standard frequency. The first bit output from the ECL/CMI interface is the most significant bit on the parallel interface, TXDT7 in eight bit mode, TXDT3 in four bit mode. The clock is generated by a phase-locked oscillator (PLO). The PLO is locked to a crystal oscillator operating at one-eighth of the standard clock frequency, 19.44MHz for OC-3, STS-3 and STM-1 and 17.408MHz for E4. This is shown in Figure 1a. An external clock signal at CKIN may also be substituted for a crystal as the reference frequency for the chip. In this mode, XTL1 and XTL2 must be configured as shown in Figure 1b. Note that the chip can be in either ECL or CMI mode when using either an external clock or a crystal for the reference. In serial mode the reference clock is output from TXCK. In parallel mode, the parallel transmit clock is output from TXCK. 2
The digital interface of the 78P2253 can be either Serial PECL, 4-bit Parallel CMOS or 8-bit Parallel CMOS.
Mode PAR/SER 8BIT/BIT Data pins Clock pins TXCKP,N RXCKP,N TXCK RXCK TXCK RXCK Clock Frequency (MHz) 155.52(Sonet) 139.264 (E4) 38.88(Sonet) 34.816(E4) 19.44(Sonet) 17.408(E4)
Serial
0
X
TXDTP,N RXDTP,N
4-bit Parallel 8-bit Parallel
1
0
TXDT[3:0] RXDT[3:0]
1
1
TXDT[7:0] RXDT[7:0]
Transmit timing is derived from either the reference clock (the crystal oscillator or CKIN), or the recovered receive clock. LLBACK and RLBACK control the local and remote loopback modes respectively.
LLBACK 0 1 X X RLBACK 0 0 1 X HUB/HOST 1 1 1 0 Transmit Clock derived from Reference Reference Receiver Receiver
Medium Choices The CMI/ECL pin selects one of two media for transmission. When the CMI/ECL pin is high, the chip is in CMI mode and a 75 coaxial cable is used as the transmission medium. In this mode, the CMIOUTP and CMIOUTN pins are active. They connect the chip to the coaxial cable through a transformer and
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
TRANSMITTER OPERATION (continued) RECEIVER OPERATION The receiver accepts serial, CMI coded data, at 155.52Mbit/s or 139.264Mbit/s from either the CMI or the ECL inputs. In CMI mode, the inputs CMIINP and CMIINN receive the input signal from a coaxial cable that is transformer-coupled to the chip. The ECL pins should be left open. In ECL mode, the pins ECLINP and ECLINN receive the input signal. In CMI mode, the received signal is equalized for dispersive cable attenuation and decoded in the CMI to binary decoder. A clock signal is recovered using a low jitter PLL circuit. FIGURE 1A: USING CRYSTAL The data is converted to binary by the CMI to Binary decoder. In serial mode, the received data is output on the RXDTP and RXDTN pins and the recovered clock is output on the RXCKP and RXCKN pins. In parallel mode, the received data is converted to parallel, eight bits if 8BIT/$BIT is high and four if it is low. The first bit received will arrive on the most significant output pin, RXDT[7] in eight bit mode and RXDT3 in four bit mode. The LOS pin goes high when the signal detector detects a loss-of-signal condition. LOOPBACK OPERATION The 78P2253 is capable of performing signal loopback in two ways The RLBACK pin selects the remote loopback mode. In this mode, the received signal is "looped back" and sent out of transmitter in place of the transmit input signal. The LLBACK pin selects the local loop-back mode, and causes the receiver to use the transmitter output signal as its input. Local loopback is disabled when HUB/HOST is low or RLBACK is high.
XTAL1 XTAL2 CKIN
XTAL1 XTAL2
17.283 MHz (E4) 19.440 MHz (Sonet)
CKIN
FIGURE 1B: USING EXTERNAL CLOCK In ECL mode the data signal is converted to CMI code by the Binary to CMI encoded. The HUB/HOST input changes the reference signal for the clock generator. In the hub mode (HUB/HOST high), the transmit clock reference is derived from either the crystal oscillator or CKIN. In host mode (HUB/HOST low), the transmit clock reference is derived from the recovered receive clock.
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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
PIN DESCRIPTION
LEGEND TYPE A CI CO DESCRIPTION Analog Pin CMOS Digital Input CMOS Digital Output TYPE PI PO S DESCRIPTION PECL Digital Input PECL Digital Output Supply Pin
TRANSMIT PINS NAME TXDTP TXDTN TXCKP TXCKN TXDT[7:0] TXCK CMIOUTP CMIOUTN ECLOUTP ECLOUTN RECEIVE PINS NAME CMIINP CMIINN ECLINP ECLINN RXCKP RXCKN RXCK RXDTP RXDTN RXDT[7:0] PIN 50 49 52 51 25 26 38 27 28 30-37 CO Receive data - Parallel Mode. In 4 bit mode RXDT[3:0] are used and RXDT[7:4] are pulled low. CO PO Recovered Receive Clock - Parallel Mode. Receive data - Serial Mode. PI PO TYPE A DESCRIPTION Receive inputs in CMI mode. Transformer coupled from the coaxial cable. Ignored in ECL mode. Receiver inputs in ECL mode. Ignored in CMI mode. Recovered Receive Clock - Serial Mode. PIN 19 20 22 23 11-18 10 60 59 56 55 PO CI CO A Transmit Data Inputs - Parallel Mode. TXDT[7:4] are ignored in 4 bit mode. Reference Clock Output - Serial mode. Transmit Clock Output - Parallel Mode. Transmit Output in CMI mode. No signal is output in ECL mode. Transmit Outputs for ECL mode. No signal is output in CMI mode. PO Transmit Clock Output - Serial Mode. TYPE PI DESCRIPTION Transmit Data Inputs - Serial Mode.
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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
PIN DESCRIPTION (continued)
REFERENCE CLOCK PINS NAME XTAL1 XTAL2 CKIN PIN 5 6 9 CI Reference clock input. The crystal oscillator connections should be left open. TYPE A DESCRIPTION Crystal Pins. Connect as in Figure 1a.
CONTROL AND STATUS PINS NAME RLBACK LLBACK HUB/HOST PIN 41 42 2 TYPE CI CI CI DESCRIPTION Loopback receiver output to transmitter input. Loopback transmitter output to receiver input. Disabled when HUB/HOST is low or RLBACK is high. In HUB mode (input high) the transmit reference clock is derived from the CKIN pin or the crystal oscillator. In HOST mode (input low) the transmit reference clock is derived from the recovered receive clock. Selects CMI (input high) or ECL (input low) modes. When high, E4 (139.264 Mbit/s) operation is selected. When low, STM-1/STS-3/OC-3 (155.52Mbit/s) operation is selected. Selects 8 bit parallel data when high and 4 bit parallel mode when low. In serial mode this pin is ignored. High during a loss-of-signal condition.
CMI/ECL E4/SONET 8BIT/$BIT LOS ANALOG PINS NAME RFO LF
1 64
CI CI CI
39
CO
PIN 46 44
TYPE A A
DESCRIPTION External reference resistor. PLL loop filter capacitor.
POWER SUPPLY PINS It is recommended that all VCC pins be connected to a single power supply plane and all GND pins be connected to a single ground plane. NAME VCC GND PIN 43 4, 7, 21, 29, 45, 47, 48, 58, 61 TYPE S S DESCRIPTION Power Supply. Ground.
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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS Operation beyond these limits may permanently damage the device. PARAMETER Supply Voltage Storage Temperature Pin Voltage Pin Current RATING 7 VDC -65 to 150 C -0.3 to (V CC+0.3) VDC 100 mA
RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. PARAMETER DC Voltage Supply, VCC Ambient Operating Temperature DC CHARACTERISTICS: PARAMETER Supply Current (Parallel Mode) Supply Current (Serial Mode) SYMBOL Icc Icc CONDITIONS Vcc = 3.3V Vcc = 5.0V VCC = 3.3V VCC = 5.0V DIGITAL INPUT CHARACTERISTICS Pins of type CI PARAMETER Input Voltage Low Input Voltage High Input Current Input Capacitance Pins of type PI PARAMETER Input Voltage Low Input Voltage High SYMBOL Vil Vih CONDITIONS Relative to Vcc Relative to Vcc -1.1 MIN NOM MAX -1.5 UNIT V V SYMBOL Vil Vih Iil, Iih Cin 2.0 -10 10 10 CONDITIONS MIN NOM MAX 0.8 UNIT V V A pF MIN NOM 140 150 210 280 MAX 165 175 245 330 mA UNIT mA RATING 3.3 0.3 VDC; 5 0.5 VDC -40 to 85C
6
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
DIGITAL OUTPUT CHARACTERISTICS Pins of type CO PARAMETER Output Voltage Low Output Voltage High Transition Time Pins of type PO PARAMETER Output Voltage Low Output Voltage High Rise Time Fall Time SYMBOL Vol Voh Tr Tf CONDITIONS Relative to Vcc Relative to Vcc MIN -1.1 NOM -1.8 -0.8 1 1 MAX -1.6 UNIT V V ns ns SYMBOL Vol Voh Tt CONDITIONS Iol = 2mA Ioh = -2mA MIN NOM 0.6 Vcc - 0.6 3.5 MAX UNIT V V ns
DIGITAL TIMING CHARACTERISTICS: Reference Clock Interface
CKIN TXCK TCK
PARAMETER CKIN to TXCK Propagation Delay
SYMBOL TCK
CONDITIONS
MIN
NOM 20
MAX
UNIT ns
7
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
DIGITAL TIMING CHARACTERISTICS Transmit Interface
TXCKP TXCKN TXDTP TXDTN TSUs THs
PARAMETER Transmit Setup Time Transmit Hold Time TXCKP,N Duty Cycle
SYMBOL TSUs THs
CONDITIONS Serial Mode Serial Mode
MIN
NOM 1.0 -0.5
MAX
UNIT ns ns
40
60
%
TXCK TXDT[7:0] TSUp THp
PARAMETER Transmit Setup Time Transmit Hold Time TXCK Duty Cycle
SYMBOL TSUp THp
CONDITIONS Parallel Mode Parallel Mode
MIN
NOM 2.5 0.1
MAX
UNIT ns ns
40
60
%
8
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
DIGITAL TIMING CHARACTERISTICS Receive Interface
RXCKP RXCKN RXDTP RXDTN
TPROPs
PARAMETER Receive Propagation Delay RXCKP,N Duty Cycle
SYMBOL TPROPs
CONDITIONS Serial Mode
MIN 40
NOM 1.0
MAX 60
UNIT ns %
RXCK RXDT[7:0] TPROPp
PARAMETER Receive Propagation Delay RXCKP,N Duty Cycle
SYMBOL TPROPs
CONDITIONS Serial Mode
MIN 40
NOM 4.0
MAX 60
UNIT ns %
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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER OUTPUT JITTER The transmit jitter specification ensures compliance with ITU-T G.823 and G.825 and ANSI T1.105.03-1994 for all supported rates. The corner frequency of the transmit PLL is nominally 3.0 MHz.
Jitter Detector Transmitter Output
20dB/decade
Measured Jitter Amplitude
200 Hz
3.5 MHz
PARAMETER Transmitter Output Jitter
CONDITION 200 Hz to 3.5 MHz
MIN
NOM
MAX 0.075
UNIT UI
TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE IN E4 MODE Bit Rate: 139.264Mbit/s 15ppm Code: coded mark inversion (CMI) The following specifications are met with the external components for E4 operation, above, and configured with a recommended 1:1 transformer as in Figure 10. With the coaxial output port driving a 75 load, the output pulses conform to the templates in Figure 4 and Figure 5. PARAMETER Peak-to-peak Output Voltage Rise/ Fall Time Transition Timing Tolerance CONDITION Template 10-90% Negative Transitions Positive Transitions at Interval Boundaries Positive Transitions at midinterval TRANSMISSION PERFORMANCE PARAMETER Return Loss CONDITION 7MHz to 240MHz MIN 15 NOM MAX UNIT dB -0.1 -0.5 -0.35 MIN 0.9 NOM MAX 1.1 2 0.1 0.5 0.35 UNIT V ns ns ns ns
10
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
V 0.60 0.55 0.50 0.45 0.40 1ns
0.1ns 0.1ns 0.35ns
T = 7.18ns (Note 1) (Note 1) Nominal Pulse 1.795 ns 1ns
0.1ns 0.35ns 0.1ns
1.795 ns 1ns
0.05
-0.05
Nominal Zero Level (Note 2)
-0.40 -0.45 -0.50 -0.55 -0.60
1ns 1.795 ns
1ns 1.795 ns
1ns
(Note 1)
(Note 1)
Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns.
FIGURE 4 - MASK OF A PULSE CORRESPONDING TO A BINARY ZERO IN E4 MODE
11
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
V 0.60 0.55 0.50 0.45 0.40 1ns
0.1ns 0.1ns 0.5ns
T = 7.18ns (Note 1) (Note 1)
1ns
0.5ns
Nominal Pulse
0.05
Nominal Zero Level (Note 2)
-0.05
3.59ns 1.35ns 1.35ns
3.59ns
-0.40 -0.45 -0.50 -0.55 -0.60
1ns 1.795 ns
1ns 1.795 ns (Note 1)
Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns. Note 5 -The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are 0.1ns and 0.5ns respectively.
Figure 5 - Mask of a Pulse corresponding to a binary One in E4 mode.
12
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER SPECIFICATIONS FOR CMI INTERFACE IN STS-3 (STM-1) MODE Bit Rate: 155.52Mbit/s 20ppm Code: coded mark inversion (CMI) The following specifications are met with the external components for STS-1 operation configured with a recpmmended 1:1 transformer as in Figure 10. With the coaxial output port driving a 75 load, the output pulses conform to the templates in Figure 6 and Figure 7. PARAMETER Peak-to-peak Output Voltage Rise/ Fall Time Transition Timing Tolerance CONDITION Template 10-90% Negative Transitions Positive Transitions at Interval Boundaries Positive Transitions at midinterval -0.1 -0.5 -0.35 MIN 0.9 NOM MAX 1.1 2 0.1 0.5 0.35 UNIT V ns ns ns ns
TRANSMISSION PERFORMANCE PARAMETER Return Loss CONDITION 7MHz to 240MHz MIN 15 NOM MAX UNIT dB
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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
V 0.60 0.55 0.50 0.45 0.40 1ns
0.1ns 0.1ns 0.35ns 0.35ns
T = 6.43ns (Note 1) (Note 1) Nominal Pulse 1.608ns 1ns
0.1ns 0.1ns
1.608ns 1ns
0.05
-0.05
Nominal Zero Level (Note 2)
-0.40 -0.45 -0.50 -0.55 -0.60
1ns 1.608ns
1ns 1.608ns
1ns
(Note 1)
(Note 1)
Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns.
Figure 6 - Mask of a Pulse corresponding to a binary Zero in STS-3 mode.
14
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
V 0.60 0.55 0.50 0.45 0.40 1ns
0.1ns 0.1ns
6.43ns (Note 1) (Note 1)
1ns
0.5ns 0.5ns
Nominal Pulse
0.05
Nominal Zero Level (Note 2)
-0.05
3.215ns 1.2ns 1.2ns
3.215ns
-0.40 -0.45 -0.50 -0.55 -0.60
1ns 1.608ns
1ns 1.608ns (Note 1)
Note 1 - The maximum "steady state" amplitude should not exceed the 0.55V limit. Overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55V and 0.6V, provided that they do not exceed the steady state level by more than 0.05V. Note 2 - For all measurements using these masks, the signal should be AC coupled, using a capacitor of not less than 0.01 F, to the input of the oscilloscope used for measurements. The nominal zero level for both masks should be aligned with the oscilloscope trace with no input signal. With the signal then applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. Any such adjustment should be the same for both masks and should not exceed 0.05V. This may be checked by removing the input signal again and verifying that the trace lies with 0.05V of the nominal zero level of the masks. Note 3 - Each pulse in a coded pulse sequence should meet the limits of the relevant mask, irrespective of the state of the preceding or succeeding pulses, with both pulse masks fixed in the same relation to a common timing reference, i.e. with their nominal start and finish edges coincident. The masks allow for HF jitter caused by intersymbol interference in the output stage, but not for jitter present in the timing signal associated with the source of the interface signal. When using an oscilloscope technique to determine pulse compliance with the mask, it is important that successive traces of the pulses overlay in order to suppress the effects of low frequency jitter. This can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the measured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. Note 4 - For the purpose of these masks, the rise time and decay time should be measured between -0.4V and 0.4V, and should not exceed 2ns. Note 5 -The inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are 0.1ns and 0.5ns respectively.
Figure 7 - Mask of a Pulse corresponding to a binary One in STS-3 mode 15
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER SPECIFICATIONS The following specifications are met with the external components. PARAMETER LOS Threshold RECEPTION PERFORMANCE Return Loss 7MHz to 240MHz 15 dB CONDITION MIN NOM 0.1 MAX UNIT V
RECEIVER JITTER TOLERANCE STS-3 and OC-3 jitter tolerance specifications are in ANSI T1.105.05-1994 and Telcordia TR-NWT-000253, Issue 2, Dec. 1991. STM-1 specifications are in ITU-T G.825. They are identical except that STM-1 specifies both jitter and wander. The E4 specifications are found in ITU-T G.823. The STM-1 specification is the tightest and covers the largest frequency range.
10000
1000
100
10
STM-1 E4
1
0.1
0.01 1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06 1.E+07
PARAMETER Receiver Jitter Tolerance Note 1: Not tested in production
CONDITION 12Hz to 178Hz 1.6mHz to 15.6mHz 125mHz to 19.3 Hz 500Hz to 6.5kHz 65kHz to 3.5MHz
MIN 2800 311 39 1.5 0.15
NOM
MAX
UNIT UI
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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics such that the receiver has the following transfer function.
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10 1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
The corner frequency of the PLL is approximately 250 kHz. PARAMETER Receiver Jitter transfer function Jitter transfer function roll-off Note 1: Not tested in production CONDITION below 250 kHz 20 MIN NOM MAX 0.1 UNIT dB dB per decade
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78P2253 E4/STM-1/STS-3/OC-3 Transceiver
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER SPECIFICATIONS FOR CMI INTERFACE The following specifications are met with the external components for E4 operation, above, and configured with a 1:1 recommended. The input signal is assumed compliant with ITU-T G.703 and attenuated by the dispersive loss of a cable. The minimum cable loss is 0dB and the maximum is shown in Figure 8. The "Worst Case" line corresponds to the01 ITU-T G.703 recommendation. The "Typical" line corresponds to a typical installation referred to in ANSI T1.102-1993. The receiver is tested using the cable model on page n. It is a lumped element approximation of the "Worst Case" line.
30
25
Attenuation (dB)
20
15
10
5
0 1.00E+05
1.00E+06
1.00E+07 Frequency (Hz) Worst Case Typical
1.00E+08
1.00E+09
Figure 8: Typical and worst-case Cable attenuation
18
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
APPLICATION INFORMATION
EXTERNAL COMPONENTS: COMPONENT Reference Resistor Filter Capacitor TRANSFORMER SPECIFICATIONS: COMPONENT Turns Ratio Suggested Manufacturer: Pulse, MiniCircuits CRYSTAL SPECIFICATIONS: E4 Operation COMPONENT Center Frequency Load Capacitor - XTAL1 to ground; XTAL2 to ground CRYSTAL SPECIFICATIONS: OC-3, STM-1, STS-3 Operation COMPONENT Center Frequency Load Capacitor - XTAL1 to ground; XTAL2 to ground VALUE 19.44 27 UNITS MHz pF TOLERANCE VALUE 17.408 27 UNITS MHz pF TOLERANCE PIN(S) RFO LF1 VALUE 31.6 150 UNITS k nF TOLERANCE 1% 10%
VALUE
UNITS 1:1
TOLERANCE 3%
19
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
APPLICATION INFORMATION (continued)
RTERM RBIAS RBIAS
FIGURE 9. PECL INTERFACE PECL INTERFACE COMPONENTS: COMPONENT Output Bias Resistor, RBIAS Termination Resistor, RTERM VCC = 5v VCC = 3.3V VALUE 250 140 100 UNITS TOLERANCE 5% 5% 5%
When the PECL signals travel one inch or less, lower power operation can be achieved by increasing RBIAS and eliminating RTERM.
20
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
VCC VCC
C18 +
C19 0.1uF
C20 0.01uF
C2 0.1uF U1
3 8 24 40 43 53 54 57
GND
4.7uF
RX1 T1 1 5 1 R1 75 1% 6 C8 VCC 0.1uF
8
VCC VCC VCC VCC VCC VCC VCC VCC
50
LOS CMIINP LF
39 44
D2 LED 1 2 C28
R12
510
J1 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
2 R12 31.6K
49 46 9 C26 27pF 5 CRYSTAL Y1
CMINN RFO CKIN XTAL1 RXCK RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 TXCK 38 30 31 32 33 34 35 36 37
1uF
2
ADT1-1WT
C1 0.1uF
Vcc U2 1 ENA OUT 5 GND
4
33 11 12 13 14 15 16 17 18 10
Crystal Osc.
Can oscillator or sigle crystal
VCC S1 1 2 3 4 5 6 7 8
C27 SW DIP-8
27pF 6 XTAL2
Isolated ground under Transformer output
J2 TX1 T2 1 6 1
16 15 14 13 12 11 10 9 R2 301 1%
1 2 62 63 64 42 41 60
CMI/ECL HUB/HOST PAR/SER 8BIT/4BIT E4/SONET LLBACK RLBACK CMIOUTP
2
2
C9 0.1uF
78P2253
FIGURE 10: RECOMMENDED APPLICATION CIRCUIT, STM-1 COAX SERIAL INTERFACE
21
4 7 21 29 45 47 48 58 61
GND GND GND GND GND GND GND GND GND
4 3 C3 ADT1-1WT 0.1uF
59
CMIOUTN
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
MECHANICAL SPECIFICATIONS
64-TQFP Mechanical Specification
22
78P2253 E4/STM-1/STS-3/OC-3 Transceiver
PACKAGE PIN DESIGNATIONS
(Top View)
CAUTION: Use handling procedures necessary for a static sensitive component.
E4/SONET
ECLOUTN
ECLOUTP
CMIOUTN
8BIT/$BIT
CMIOUTP
PAR/ SER
ECLINN
ECLINP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CMI/ECL HUB/HOST VCC GND XTAL1 XTAL2 GND VCC CKIN TXCK TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND GND RFO GND LF VCC LLBA CK RLBACK VCC LOS RXCK RXDT0 RXDT1 RXDT2 RXDT3 RXDT4
TXDTN
RXDTN
TXDT1
TXDT0
VCC
RXDT7
RXTD6
TXCKN
RXTDP
64-Pin TQFP (JEDEC LQFP) 78P2253-I64GT
ORDERING INFORMATION
PART DESCRIPTION 78P2253 64- Pin Thin Quad Flatpack 78P2253-IGT 78P2253-IGT ORDER NUMBER PACKAGING MARK
Advanced Information: Indicates a product is either in prototype testing or undergoing design evaluation prior to full production release. Specifications are based on design goals or preliminary evaluation and are not guaranteed. Small quantities are usually available and TDK Semiconductor Corporation should be consulted for current information. No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our web site at http://www.tsc.tdk.com or contact your local TDK Semiconductor representative. TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 (c)2000 TDK Semiconductor Corporation 11/08/00- rev. D
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RXCKN
RXCKP
RXDT5
GND
TXCKP
TXDTP
GND
CMIINN
CMIINP
GND
GND
VCC
VCC
VCC

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